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[VHDL-FPGA-Verilog] adder16bit

Description: 16位高速加法器，采用verilog语言编写，已经成功仿真，能够运行-16 high-speed adder using Verilog language has been successful simulation can be run
Platform: | Size: 2048 | Author: modelsims | Hits:

[Windows Develop] lab7

Description: 利用verilog语言设计32位进位选择加法器。实现高速计算功能。-Use verilog language design 32 carry select adder. High-speed computing.
Platform: | Size: 502784 | Author: 张宇舟 | Hits:

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